This application is a continuation-in-part of U.S. patent application Ser. No. 09/396,165, filed Sep. 14, 1999 now abandoned.
1. Field of the Invention
The present invention relates to electrostatic discharge (ESD) protection, and more particularly, to a complementary metal-oxide semiconductor (CMOS) silicon-control-rectifier (SCR) structure suitable for protecting an internal circuit from ESD.
2. Description of the Prior Art
Progress in semiconductor technology has decreased the dimensions of many semiconductor devices. As very large scale integration (VLSI) circuit geometry continues to shrink, the corresponding gate oxide thickness has also continued to decrease. This decrease in thickness, relative to breakdown voltage, has resulted in an increased susceptibility to damage from the application of excessive voltages. For example, an electrostatic discharge (ESD) event is capable of developing such an excess voltage. During an ESD event, charge is transferred between one or more pins of the device and another conducting object in a time period that is typically less than one microsecond. This charge transfer can develop voltages that are large enough to break down insulating films (e.g., gate oxides) on the device, or can dissipate sufficient energy to cause electrothermal failures in the device. Such failures include contact spiking, silicon melting, or metal interconnect melting.
Accordingly, ESD protection and its impact on the reliability of IC products in submicron CMOS technologies has become a primary concern. The resulting protection circuits may typically be connected to all Input/Output (I/O) pads of an integrated circuit (IC) to safely dissipate the energy associated with ESD events without causing any damage to the circuitry internal to the device. Protection circuits have also been connected to power supply pads, or between power supply buses to prevent such damage to internal circuits.
An ESD protection circuit that includes a silicon-control-rectifier (SCR) is considered to have very good electrostatic discharge performance. Since the SCR ESD protection circuit has a low snap-back holding voltage of about 1–5 volts and a low effective resistance of about 1–3 Ohms, it provides a very good discharge condition for the electrostatic current. However, there is one inherent constraining design factor for the SCR used in ESD protection circuits for sub-micron semiconductor devices. The trigger voltage for SCRs in sub-micron CMOS devices is in the range of 30 to 50 Volts. The typical thickness of gate oxide layers in CMOS fabrication processes employing a resolution of 0.6–0.8 microns is about 150–200 angstroms. Considering a dielectric breakdown strength of 10 MV/cm for typical SiO.sub.2.material, the gate oxide layers in these sub-micron CMOS devices would be destroyed by a voltage of about 15–20 volts. Therefore, SCRs with a trigger voltage in the range of 30–50 volts must be fitted with other protection components so that they can provide protection for gate oxide layers in sub-micron CMOS IC devices.
Efforts have been made to lower the trigger voltage of SCRs in the ESD protection circuits for the sub-micron CMOS device. The trigger voltage should be reduced to below the dielectric breakdown voltage of the gate oxide layers of the CMOS device, so that the ESD protection circuits can provide protection for the CMOS device before being damaged themselves. Several ways to lower the trigger voltage of SCRs have already been proposed.
In one common approach, A. Chatterjee and T. Polgreen proposed a low-voltage trigger SCR (LVTSCR) configuration in “A LOW-VOLTAGE TRIGGERING SCR FOR ON-CHIP ESD PROTECTION AT OUTPUT AND INPUT PADS,” IEEE Electron Device Letters, 12 (1), 1991, pp.21–22. In their disclosure, Chatterjee and Polgreen employed a short-channel NMOS transistor coupled to an SCR to form the low-voltage trigger SCR having a trigger voltage that is about equal to the breakdown voltage of the short-channel NMOS transistor.
Referring to FIG. 1A, a LVTSCR is placed in between an Input/Output pad 10 and an internal circuit 11 to be protected. The internal circuit 11 is tied to the Input/Output pad 10 via a conducting line 12. An SCR device serves as the main component in a protection circuit. In the drawing, the SCR device consists essentially of a PNP bipolar junction transistor T.sub.1 and an NPN bipolar junction transistor T.sub.2. The collector of the PNP transistor T.sub.1 is connected together with the base of the NPN transistor T.sub.2, forming a cathode gate identified by the node 13. The cathode gate 13 is coupled to the emitter of the NPN transistor T.sub.2, via a spreading resistor R.sub.p, constituting a cathode 14 which is connected to a Vss terminal of the CMOS IC device. The base of the PNP transistor T.sub.1 is connected together with the collector of NPN transistor T.sub.2 to form an anode gate identified by the node 15. The anode gate 15 is coupled to the emitter of the PNP transistor T.sub.1, via a spreading resistor R.sub.n, constituting an anode 16 which is connected to the conducting line 12. To achieve a reduction of the SCR trigger voltage from about 30–50 volts to a level less than the NMOS breakdown voltage of less than 15 volts, an NMOS-like structure N.sub.1 is incorporated in the SCR device as a trigger.
FIG. 1B shows a cross sectional view of a LVTSCR integrated circuit device 20 fabricated from a semiconductor substrate 21 of a first conductivity type, such as P-type conductivity, with various diffusions and circuits components formed thereon to provide protection against ESD damage due to excessive stresses. Accordingly, a thin-oxide NMOS field-effect transistor (MOSFET), is shown in the LVTSCR integrated circuit device 20 in the form of an N-channel device, composed of N+ regions, 22 and 23, having a gate electrode 24 with a thin oxide 25 therebetween. The outer N+ region 22 is coupled to an adjacent out P+ conductivity region 26 by a contact or bus 27 which is connected to a negative voltage source VSS or ground. The Vss source is also coupled to the gate electrode 24 to keep the LVTSCR OFF during normal operation. To complete the LVTSCR, an N-well 28 is provided in substrate 21 that substantially overlaps N+ region 23 and extends laterally beyond a second N+ region 29 which is coupled to an adjacent inner P+ conductivity region 30 by a contact or bus 31 connected to a Pad/Internal Circuit.
There exists a danger, since the N-well is lightly doped, that the SCR turn-on voltage may still be so high that the gate oxide of NMOS devices may become damaged. Thus, the LVTSCR device turn-on voltage is dependent on the NMOS breakdown voltage. It is therefore desirable to be able to reduce the trigger voltage required to turn ON a protective SCR as much as possible. Moreover, ESD protection by using the LVTSCR device is easily to be restricted in CMOS process, that is because the channel length of the additional NMOS device needs to be smaller than the output NMOS of the SCR for making sure the additional NMOS device breakdown before the NMOS device in CMOS output.
It is therefore an object of the present invention to provide an enhanced ESD protection performance apparatus for protecting VLSI circuits and particularly CMOS devices by reducing the trigger voltage required to turn ON a protective SCR.